1. Field of the Invention
The present invention generally relates to semiconductor processing technologies and, more specifically, to a post-etch deposition on a dielectric film in semiconductor processing.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g. sub-micron dimensions), the materials used to fabricate such components contribute to their electrical performance. For example, metal interconnects with low resistance (e.g., copper and aluminum) provide conductive paths between the components on integrated circuits.
Copper is particularly advantageous for use in interconnect structures due to its desirable electrical properties. Copper interconnect system are typically fabricated using a damascene process in which trenches and vias are etched into dielectric layers. The trenches and vias are filled with copper which is then planarized using, for example, a chemical-mechanical planarization (CMP) process.
Copper interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or thickness of the insulating material has sub-micron dimensions, capacitive coupling may potentially occur between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit. In order to prevent capacitive coupling between adjacent metal interconnects, low dielectric constant (low k) insulating materials (e.g. dielectric constants less than about 4.0) are needed.
During fabrication of the interconnect structure, the dielectric etch processes (e.g., reactive ion etch (RIE), inductively coupled plasma (ICP) etch, and the like) are generally used to form the contact holes and trenches in the low-k insulator layers. However, these etch processes have adversely effected many low-k dielectric materials. For example, silanol terminated group, e.g., Si—OH bonds, may accumulate on the surface of the etched low-k film, thereby causing the carbon depletion at the film surface. Carbon depletion may cause the film surface to absorb moisture when exposed to an ambient environment. The absorbed moisture causes the dielectric constant of the low-k material to undesirably increase, resulting in a “k loss,” in the materials dielectric properties. As a result, cross-talk and RC delay may increase after the etching process.
Therefore, there is a need for an improved process for etching low-k materials.